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78M6618 Data Sheet
DS_6618_005
The SPI port supports data transfers at up to 1 Mb/s. The SPI commands are described in Table 1 and
Table 1: SPI Command Description
Command
11xx xxxx ADDR D0 ... DN
1100 0000 ADDR D0 ... DN
10xx xxxx ADDR D0 ... DN
1000 0000 ADDR D0 ... DN
Description
Output data on PSDO is read from RAM starting with byte at ADDR.
ADDR will auto-increment until PCSZ is raised.
MPU SPI interrupt is generated
Output data on PSDO is read from RAM starting with byte at ADDR.
ADDR will auto-increment until PCSZ is raised.
No MPU SPI interrupt is generated
Input data on PSDI is written to RAM starting with byte at ADDR.
ADDR will auto-increment until PCSZ is raised.
MPU SPI interrupt is generated
Input data on PSDI is written to RAM starting with byte at ADDR.
ADDR will auto-increment until PCSZ is raised.
No MPU SPI interrupt is generated
CMD
ADDR D0 ... DN
CMD and ADDR are available to the CPU in IORAM
D0 … DN are ignored.
MPU SPI interrupt is generated
SERIAL READ
8 bit CMD
16 bit Address
DATA[ADDR]
DATA[ADDR+1]
PCSZ
Extended Read . . .
0
7
8
23
24
31
32
39
PSCK
(From Host) PSDI
(From 6531) PSDO
x
C7
C6
C5
C0
HI Z
A15
A14
A1
A0
x
D7
D6
D1
D0
D7
D6
D1
D0
SERIAL WRITE
8 bit CMD
16 bit Address
DATA[ADDR]
DATA[ADDR+1]
PCSZ
Extended Write . . .
0
7
8
23
24
31
32
39
PSCK
(From Host) PSDI
x
C7
C6
C5
C0
A15
A14
A1
A0
D7
D6
D1
D0
D7
D6
D1
D0
x
(From 6531) PSDO
HI Z
Figure 4: SPI Slave Port: Typical Read and Write Operations
Since the addresses are in 16-bit format, any type of XRAM data can be accessed: CE, MPU or IORAM
but not SFRs or the 80515-internal register bank. See the 78M6618 Programmer’s Reference Manual for
more information regarding the mapping and use of SPI functions.
1.19 Test Port
One out of 16 digital or 8 analog signals can be selected to be output on the TMUXOUT pin. See the
78M6618 Programmer’s Reference Manual for more information regarding the use of TMUXOUT.
12
Rev. 1.4
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相关PDF资料
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